FIG. 1 illustrates a conventional 1T, 1C DRAM cell 10 that contains a capacitor 12 for storing the data and a pass transistor 11 controlled by a Word Line (WL) that connects the storage node to the Bitline (BL). The charge stored on the capacitor will, of course, leak away and the charge must be refreshed. The refresh cycle consists of a read operation that destructively reads the stored data followed by a write operation that writes the data back in the cell with the maximum charge that the apparatus allows. As is well known, the cell may not be written to or read from during the course of the refresh operation.
FIG. 2 shows a transistor level schematic of a multi-port 3T1C DRAM gain cell. These cells may be written to and read from independently, since they have separate read and write ports (a read port with a Read Word Line, RWL, and a Read Bitline, RBL, and a write port with a Write Word Line, WWL, and a Write Bitline, WBL). They also must be refreshed, since the data bit is also stored in a capacitor that has a finite leakage.
The NMOS transistor 24 couples the storage node 22 to the write bitline WBL for a write operation, when the write wordline WWL goes high. The storage node 22 may preferably have a capacitor 25 to keep the data bit. The data bit stored in a storage node 22 can be read out to the read bitline RBL when the read wordline RWL goes high. If the storage node 22 keeps a high data, two NMOS transistors 21 and 23 are both on, discharging the RBL. If the storage node keeps a low voltage, the NMOS transistor 23 is off, keeping the RBL at the precharged voltage.
The 3T gain cell can simultaneously realize a read operation by using RWL and RBL, and a write operation by using WWL and WBL, thereby providing a solution for a high performance memory system. It does, however, require a refresh to maintain the data. Unlike a conventional 1T cell in FIG. 1, the 3T gain cell requires to read the data bit first by activating a RWL, and then rewrite a data bit to the cell by activating WWL. This results in a 2 cycle refresh, reducing memory availability.
The art could benefit from a 3T1C cell that has a single cycle refresh mode that improves the memory availability for normal read and write operations.